Meaning Of Each Of The Four Stages In The Mesi Protocol

Running head: MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL 1

Meaning Of Each of the Four Stages In The Mesi Protocol

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MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL 2

ASSIGNMENT 10

REVIEW QUESTION 17.6: Meaning of each of the four stages in the MESI protocol

Modified: Modification is done to the cache line that is contained in the cache memory. This is

not the same as the main memory only this cache has it. Sometime in the future, necessity of the

cache comes when data is written on the main memory, before any other invalid (already read)

main memory state to be allowed. Writing back changes the state of the line to share.

Exclusive: The main memory is identical to the cache line found in the cache. However, the main

memory is not found in any cache location. Read request at any time may change it to shared

state. Furthermore, when writing to it you may change it to Modified state.

Shared: The cache line may be similar to the main memory and any cache location may contain

it. This implies that the particular cache line may be stored in different machine caches and its

clean, meaning that it matches with the main memory.

Invalid: Invalid data is contained in the cache line.

Review Questions: 17.9: Differences among UMA, NUMA, and CC-NUMA?

In UMA, the same time is required to access a memory unit to all memory regions by a

processor, NUMA has variable access time of the memory unit depending on the main memory

region that is being accessed while CC-NUMA model, the memory is accessed by the

processor.

In UMA, different processors have the same access time,in NUMA different processors have

variable access time while the access time is the same in CC-NUMA because a cache is unique

to each processor.

In UMA, any memory part can be accessed by any processor using loads and store instructions.

In NUMA, any processor can access any main memory part while in CC-NUMA, various

caches maintain the same cache coherence of different processors.

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL 3

Problem 17.4

1. P2 reads x.

 Taking that both processors consist of invalid copies initially.

 Processor 2 reads the value X from the main memory, changing its state to Exclusive

from Invalid.

 Exclusive state implies that the cache line at the current cache only, it is present and

matches with the main memory.

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL 4

2. P1 writes to x (for clarity, label the line in P1’s cache x=).

 An invalid loop is contained in the processor 1 initially.

 The state is changed from invalid to Exclusive when an attempt is made to write

the memory location X

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL 5

3. P1 writes to x (label the line in P1’s cache x).

 Processor 1 in Exclusive state while processor 2 in Invalid state.

 Modification to loop is made when processor 1 tries to overwrite memory location.

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL 6

4. P2 reads x.

Processor 2 tries to read the memory location written by processor 1

Processor 1 blocks reading the x copy, then updates the fresh copy (x

”

) to the main memory from

cache memory.

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL 7

17.5

With two cache coherence protocols;

Cache coherence protocol states have invalid and valid states only, also called Invalid-Modify

protocol (MI protocol) which acts as a basic protocol in cache coherence.

In general, the use of cache coherence protocols is to maintain coherence in shared memory

multiprocessor architecture.

The invalid state does not read line by the processor; neither does it writes to the line by the

operation of the processor it is performed. Therefore if the block is absent, the invalid state will

be looped.

The advantages are that it is easy to implement, there are only two transient states and the

burdens of cache coherence will be reduced due to the two states.

With three cache coherence protocols;

The three states are Invalid, Shared and Exclusive.

Invalid state neither reads nor writes operation to or from other states. Exclusive state looks after

broadcasting of the messages that is not necessary, meaning it only looks after valid sent

messages while shared state can be shared while in other processors cache.

MESI (Modifies, Exclusive, Invalid and shared) protocol

In this protocol, the means to indicate cache block is identified and clean is unavailable. To

overcome this, an extra state is added called exclusive state. Back message in modified state is

sent to replace the cache line.

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL 8

17.11

From above, two separate threads execution have been shown where A is a single thread and B is

another separate one. The above issue diagram shows the separate threads flow ,providing

continuous execution of multiple threads concurrently.

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL 9

b) Assuming the two threads are executed in parallel on different multiprocessor chips

Each of the two cores in the chip will be executed using the simple pipeline mechanism. As

drawn below ,since the both of the two pipelines are processing at the same time using separate

processors present on the same chip .

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL

c)Assuming that tread A required a latency of two clock cycles before the execution of the

respective instruction which is denoted as A15.It is possible that the mechanism for performing

the interleaving operation is using the similar thread for two different successive clock cycles

wherever needed .If the two issues superscalar architecture is used for the operation of

multithreading using data dependencies than the instruction issue diagram along with the

pipeline execution diagram is shown below:

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL

d)The mechanism for performing the interleaving operation is using the similar thread for the

two different successive clock cycles wherever needed. When the super scalar architecture

implementation is blocked ,the respective instruction issue diagram is shown below:

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL

e) SMT is a technique for improving the overall efficiency of superscalar CPUs with hardware

multithreading. It permits using multiple but independed threads of execution to better utilize the

resources provided by modern processor architectures.

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL

Review question 18.6

Provided that the number of cycles that are needed for execution for an integer instruction is 1

cycle, floating point instruction is 4 cycles and memory instruction is 3 cycles.

Each cycle can execute an thread and given that they are in a pipeline fashion. Thus the

maximum cycles are 4 for floating point instruction. The smallest number of threads is required

to be completely utilized by giving an instruction to every cycle for our program is 4 threads.

MEANING OF EACH OF THE FOUR STAGES IN THE MESI PROTOCOL

c) Yes, fewer threads can reach a peak performance. The latency of a floating point command

can be hidden ,this can be done through changing the add instructions between floating point and

store instructions.# threads are required for this procedure ,which move third load instruction one

step up to follow the second load instruction ,thus the requirement will be reduced to only 2

threads.

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