Midterm Report

Processor Prototyping Laboratory

October 15th, xxxx

Overview

This midterm report will analyze the overall performances of our single-cycle

processor as well as our pipelined processor designs implemented with the MIPS

instruction set. Both designs are design to complete the same tasks, but with varying

performance results. The single cycle implementation will complete instruction sets

reliably with no repercussions of hazards, but at a slower maximum frequency. The

pipeline design completes the same tasks within a lower execution time than the single

cycle implementation but has to deal with the concepts of hazards. Ideally, the pipeline

design increases the throughput of the processor, while maintaining similar CPI as the

single-cycle counterpart. With the implementation of a hazard and forwarding unit, our

design also detects the presence of structural and data hazard and performs the correct

logical actions accordingly. To compare our designs, we are running a mergesort

assembly file. This file is beneficial as a benchmarking test because it requires reading

from and writing to memory, both R and I types of instructions, and has instructions that

rely on the result of the instruction immediately before, which is necessary to thoroughly

test the pipeline design.

The performance data gathered after running each processor to perform the

same task validates the intention of our designs. The pipeline’s maximum frequency

and highest achieved frequency is approximately twice that of the single cycle design,

with average instructions per cycle dropping to about half in comparison to the single

cycle. Because the pipeline deals with hazards through stalls, the average latency per

instruction is higher than the single cycle, and more resources are required to

synthesize the design on an FPGA board. Overall, however, the pipeline design

executes the process in less time than the single cycle, which is the outcome we are

after when implementing a pipelined processor design.

Processor Design

Single Cycle

Pipeline Hazard and Forwarding Unit

Results

Single Cycle Processor

Pipeline Processor

Max possible frequency

31.05 MHz

67.84 MHz

Highest achieved

frequency

1/20ns = 50 MHz

1/10ns = 100 MHz

Average instructions per

clock cycle

5399

instructions/12661

cycles = 0.4264

5399

instructions/21932

cycles = 0.2462

Latency of one instruction

0.4264

1.231

Total execution time of

program

253,240 ns

219,330 ns

FPGA resources required

3115

4484

Max possible frequency - obtained from synthesizing, simulating, and then

reading system.log file

Highest achieved frequency - the frequency corresponding to the lowest

clock period achieved in the testbench

Average instructions per clock cycle - number of instructions obtained from

running “sim -t” after loading mergesort, cycles obtained from running

“make system.sim”, highest achieved frequency obtained from [instructions

/ cycles]

Latency of one instruction - [Average instructions per clock cycle] * [(single

cycle ? 1 : 5)]

Total execution time of program - Obtained by running ‘make system.sim’

FPGA resources required - Total logic elements from system.log

Conclusions

As briefly mentioned in the overview, the benefits of the pipeline design

over the single cycle design are quantitatively noticeable in the results.

The pipeline maximum frequency is about 68 MHz, which is over twice as

much as the 31 MHz actualized by the single cycle. This implementation of

mergesort has 5399 lines, which when divided by the number of cycles for

each design gives the average instructions per clock cycle. As expected,

this number is higher for the pipeline, because more clock cycles are

needed to deal with hazards.

The latency per instruction is then calculated by multiplying the

average instructions per clock cycle by the number of stages in the design.

For the single cycle, there’s a single stage, but for our version of the

pipeline, there are five stages. Ultimately, the total program execution time

for the pipeline is 219,330 ns, which is less than the 253,240 ns required by

the single cycle. This outcome is desirable, but comes at a cost, as more

resources (~130%) are needed to map the pipelined design to an FPGA

compared to a single cycle processor implementation.

Place new order. It's free, fast and safe

Paper type

Deadline

Page count

550 words

Total price: $ 15.00

Our customers say

Jeff Curtis

USA, Student

"I'm fully satisfied with the essay I've just received. When I read it, I felt like it was exactly what I wanted to say, but couldn’t find the necessary words. Thank you!"

Ian McGregor

UK, Student

"I don’t know what I would do without your assistance! With your help, I met my deadline just in time and the work was very professional. I will be back in several days with another assignment!"

Shannon Williams

Canada, Student

"It was the perfect experience! I enjoyed working with my writer, he delivered my work on time and followed all the guidelines about the referencing and contents."