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The von Neumann computer model

This model will introduce the basic computer and show the operation of the same through

the specified register transfer modules. The organization of a computer is specified by the internal

registers, the control structure, the timing and the instruction sets utilized. The advantage of this

detailing is the ease of illustration without the complications. The manipulation of the data stored

in the registers has been used in the definition of digital systems. From this, we realize that a

program is a set of instructions that define the operations, operands and the sequence with which

the operations occur. The computer will read the instructions and then transfer to the control

1. Instruction code

These are a group of bits that are utilized in the instructing of the computer to perform a

particular operation.

2. Operation code

This is the group of bits in an instruction set that defines the operation to be carried out by

the computer like add, subtract, multiply, complement and shift. The bits in the operation code is

dependent on the number of the operation available to the computer. But the operation code should

always consist of at least n bits for any 2n unique operations. For a computer with 64 unique

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operation where one is ADD then the operation code will be a six bit with the following bit

configuration 110010.

After every operation, data must be stored in the registers or in the memory. Instruction

sets, in this case, will always define the instruction set and the register of the memory for the

storage of the result. The registers can be specified by defining a binary code of k bits that specifies

the register e.g. 2k register.

3. Stored program organization

Computers are organized simply by having one processor register and the instruction code

format with two parts. The first part will define the operation to be carried out while the second

part will specify the address. The memory address will tell the control where to locate the operand

hence will be read and then used as data in the operation. Instructions are usually stored on one

side of the memory while the data is stored in another. For instance, a memory unit with 4096

words requires 12 bits to specify the address since 212 = 4096. If the instructions are stored using

16 bits memory word, then there are four bits available for the bits of the operation code. The

control will read a 16-bit instruction from the program section of the memory and then uses the

12-bit address of the instruction to read the 16-bits operand from the data part of the memory.

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Figure 1: Stored program organization

i. Accumulator (AC)

These are registers that are found in computers with a single processor register. The

operation usually occurs with the memory operand and the content of the AC. Operations like the

complement AC, clear AC, or increment AC only operates on the data stored hence they do not

require the operand hence the memory is used for other purposes.

ii. Indirect Address

Sometimes the address bit of an instruction code can be utilized as an actual operand for

convenience. This case results in the intermediate code when the second part of the instruction

specifies the operand. In the case of indirect address the bits in the second part of the instruction

will define an address of a memory word where the address of the operand exists. In cases of

computation-type instruction or where there is a branch-type instruction hence these addresses are

defined by effective address.

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Figure 2: Direct and Indirect address

4. Registers

These are the memory location where the computer instructions are stored. These are read

and executed sequentially. There is always the need to provide a register in the control unit for the

storage of the instructions code this is after it has been read from memory. The memory unit has a

capacity for 4096 words each containing 16 bits. Twelve bits of the instruction word are used to

specify the address of the operand; three bits are for the operation portion of the instruction while

one is for specifying the direct or indirect address.

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Figure 3: Registers of a basic computer

i. Program Counter (PC)

This register has 12 bits that are utilized in the holding of the address of the next instruction

to be executed. Together with the IR, the PC is a control unit register. The Pc is characterized by

a counting sequence that causes the computer to read the sequential instructions.

ii. Input/output registers

There are two input/output registers that hold characters for the input device and the output

device. The INPR and the OUTR hold 8-bit characters.

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Figure 4: Computer registers and memory

5. Bus system

A basic computer has eight registers, control unit, and a memory unit. The bus system

provides the paths necessary for the relay of data between registers and also between the registers

to the memory. To avoid the use of excessive wires, the common bus system is utilized in this

case. The bus system can be constructed from a multiplexer or three-state buffer gates. The out of

seven registers and the memory are all connected to the common bus. The output on the bus will

be selected based on the binary value of the selection variable which are S2, S1, and S0. For

instance, the output of the DR to be placed in the bus line will be S2S1S0 = 011whixh is the value

for decimal 3. The register whose load input (LD) has been activated will receive the data from

the bus in the next clock pulse transition. The input and the output data of the memory are usually

interfaced with the common bus while the memory address will be interface to AR. The AR will,

therefore, be utilized in the specifying of the memory address.

The content of any register can be applied to the common bus and the operation performed

in the adder and the logic circuit in the same clock cycle.

6. Computer Instructions

The basic computer can execute three instruction sets the memory reference, register

reference, and the input-output instruction. The opcode portion of the instruction has three bits and

the remaining 13 bits are dependent on the opcode encountered. A memory reference instruction

utilizes 12 bits to determine the address and one bit to define the addressing mode I. The I is equal

to 0 in thee direct address and 1 for the indirect address. The register reference instruction is

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recognized by the opcode 111 with a 0 in the leftmost bit i.e. bit 15of the instruction. The register-

reference instruction will always specify an operation on or a test of the AC register.

A computer can recognize the type of instructions from the four bits in position 12 to 15 of

the instruction. For memory reference, the opcode bits between 12 and 14 are always not equal to

111. The bit at position 15 is the addressing mode I. For the register-reference type operations the

opcode is equal to 111, and the addressing mode bit is 0. The bit in case the addressing mode bit

is 0 then the operation is input-output.

Figure 5: Computer instructions

7. Timing and control

The timing of the registers is controlled by a master clock generator. The clock pulses are

applicable to all flip-flops and the registers in the system. The clock pulse will not vary the state

of the register, this will happen only if the register is enabled by the control signal.

There are two kinds of control in a computer organization. The hardwired control this is

where the logic of the organization is applied by flip-flops, gates, decoders, and any other digital

circuit. It can be optimized occasionally to enable a fast mode of operation. Microprogrammed

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control is where the control instruction is stored in the memory that is located in the control unit.

The control memory will be commanded to initiate the appropriate sequence of operation.

8. Control unit

The control unit is composed of two decoders, sequence counter, and several control logic

gates. Any instruction read from memory will be stored in the instruction register (IR). The

operation code will be decode using the 3 x 8 decoder while the output is defined by D0 to D7.

The output of the counters will be decoded to a 16 timing signal T0 to T15.

Figure 6: the control unit of the computer.

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Works Cited

Ltd, The teacher.Info. Von Neumann architecture. 17 September 2016. Internet source. 27

November 2016.

M, D Godfrey, and F Hendry D. "The computer as Von Neumann planned it." IEEE Annals of the

History of Computing (1993): 11-21. Print.

Mano, M Morris. Computer system architecture. Prentice Hall: International Edition, 1993. Print.

Schulte, Eric. NonVon Neumann Computation. Survey. Albuquerque: University of New Mexico,

2010. Print.

Stallings, William. Computer organization and architecture designing for performance. New York:

Pearson Publishers, 2013. Print.

University, Simon Fraser. Overview of Von Neumann Architecture. 12 September 2010. Internet

source. 27 November 2016.

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